17. XER (Fixed-Point Exception Register)

3.2.2 Fixed-Point Exception
Register
The Fixed-Point Exception Register (XER) is a 64-bit
register.

The bit definitions for the Fixed-Point Exception Register
are shown below. Here M=0 in 64-bit mode and
M=32 in 32-bit mode.

The bits are set based on the operation of an instruction
considered as a whole, not on intermediate results
(e.g., the Subtract From Carrying instruction, the result
of which is specified as the sum of three values, sets
bits in the Fixed-Point Exception Register based on the
entire operation, not on an intermediate sum).

Bit(s Description:

0:31 Reserved

32: Summary Overflow (SO)
is set to 1 whenever an instruction (except mtspr) sets the Overflow bit.

33: Overflow (OV)
The Overflow bit is set to indicate that an overflow has occurred during execution of an instruction

34: Carry (CA)
ADDC,SUBFC, ADDE, SUBFE set it to 1 if there is a bit carry out of bit M
SRA* set it to 1 if any 1-bits have been shifted out of a negative operand

35:43 Reserved

44: Overflow32 (OV32)

V32 is set whenever OV is set

45: Carry32 (CA32)
CA32 is set whenever CA is set

46:56 Reserved

57:63 This field specifies the number of bytes to be
transferred by a Load String Indexed or Store
String Indexed instruction.