rldicl RA,RS,SH,MB (Rc=0)
rldicl. RA,RS,SH,MB (Rc=1)
30 RS RA sh mb 0 sh Rc
0 6 11 16 21 27 30 31
The contents of register RS are rotated64 left SH bits. A
mask is generated having 1-bits from bit MB through bit
63 and 0-bits elsewhere. The rotated data are ANDed
with the generated mask and the result is placed into
register RA.
Special Registers Altered:
CR0 (if Rc=1)
Extended Mnemonics:
Examples of extended mnemonics for Rotate Left Doubleword
Immediate then Clear Left
Extended: Equivalent to:
srdi Rx,Ry,n rldicl Rx,Ry,64-n,n
NOTE:
left shif n bit <=> right shift (64-n) bit in rotate64 mode
left shif n bit <=> right shift (32-n) bit in rotate32 mode
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